? 2004 fairchild semiconductor corporation an010938 www.fairchildsemi.com fairchild semiconductor application note june 1991 revised february 2004 AN-784 f100k ecl dual rail translators AN-784 f100k ecl dual rail translators introduction the complex electronic systems being designed today often require mixed technologies to incorporate the most efficient balance of performance, speed, power, and cost. in order for one technology to communicate with the other, an interface is needed. one of the most common mix of technologies seen today is high speed ecl with the slower, but very popular ttl and cmos. to make this interface as quick and clean as possible, level translators are used. this applications note will discuss ecl to ttl and ttl to ecl level translators available from fairchild semiconduc- tor?s f100k ecl 300 series product line. focus will be on dual rail translators (translators which require both ecl and ttl power supplies for normal operation), their differ- entiating features and possible uses. translator selection fairchild semiconductor offers translators of all different types. table 1 shows the ttl to ecl and ecl to ttl translators that are presently available. the first 300 series translators designed were the 100324 and 100325. with these devices, unidirectional translation is possible in either direction (ttl to ecl with the 100324, ecl to ttl with the 100325). as systems and data widths become larger, more bits need to be translated. this need was satisfied with the introduction of 8- and 9-bit translators. the 8-bit translator (100329) also offer bidirectional translation functionality for applications which require two way communication. in many cases, communication over significant distances is needed in noisy environments. in applications where high output drive is needed after an ecl to ttl translation the 9-bit 100395 can be used. the 64 ma i ol output current capability is ideal for driving long lines and achieving faster switching times by discharging the line it is tied to faster when in the low output state. these outputs are also capable of driving higher fanouts than the lower output cur- rent devices. if the designer only has a + 5v supply available (i.e., an additional ecl supply cannot be used), single rail transla- tors can be used. for more information on single rail trans- lation refer to applications note an-780 ? operating ecl from a single positive supply ? . table 1. 300 series dual rail translators note 1: v bb output available for 100325 mecl ? is a trademark of motorola, inc. features 100324 100325 100329 100395 data bits 6 6 8 9 ecl to ttl x x x ttl to ecl x x latched registered x x ecl differential out in (note 1) ecl drive (ohms) 50 50 ecl cutoff x ttl drive i ol /i oh (ma) 20/ ? 2 24/ ? 3 64/ ? 15 ttl 3-state x x ecl control pins x x ttl control pins x tpd ecl to ttl (ns max) 4.8 7.7 6.4 tpd ttl to ecl (ns max) 3.0 3.9 i ee (ma max) ? 70 ? 37 ? 199 ? 67 i cc (ma max) 38 65 74 65
www.fairchildsemi.com 2 AN-784 translator operation speed advantages designers who have primarily a ttl system will often use ecl in areas such as clock distribution, backplanes, and differential data transmission where speed is most impor- tant. this can be accomplished by level translating from ttl to ecl, performing the desired ecl operation, and then translating back to ttl. as intimidating as this approach sounds, the propagation delay savings gained can be very significant. consider as an example the ttl ? error capture circuit ? shown in figure 1 and the same func- tion performed using ecl shown in figure 3. in figure 1, a ttl system with control lines cr0 and cr1 is being moni- tored for errors. the error capture circuit consists of a buffer, decoder, and six counters. the buffer transfers sig- nals from the control lines to the inputs of the decoder. the decoder determines which type of error is present and then feeds into a 2 stage counter to keep track of how many times a particular error occurs. table 2 gives conditions for all possible levels on the con- trol lines. when a counter reaches a terminal count of 256 for any type of error, a signal is fed to the ttl controller which initiates a service routine for that particular type of error. for the pdip devices shown in figure 1, the maxi- mum propagation delay at room temperature for the error capture circuit is approximately 51 ns. table 2. system errors figure 1. ttl error capture circuit a significant amount of time can be saved by using transla- tors and performing the error capture with ecl. in figure 3, an ecl error capture solution is implemented. in this case, a 100324 ttl to ecl translator is used to buffer the control line signals and provide the required ecl voltage levels. data is then fed into the 100370 decoder and inverted for counter input. as in the ttl circuit (see figure 1), when the count reaches 256 for any type of error, a signal is fed into the controller for service routine activation. the ecl signal is first converted to ttl by use of the 100325 before being transferred to the controller. the error circuit for fig- ure 3 has a maximum propagation delay (using cdip pack- age at 25 c) of approximately 20 ns. a comparison of the ecl and ttl error capture circuits shows that ecl offers a 31 ns advantage in speed over the equivalent ttl design. this is a savings of more than half of the entire ttl timing budget. another benefit of using ecl in high speed applications is that as frequency increases, ttl power increases while ecl power remains constant. in fact, as system bandwidth requirements exceed 50 mhz, ecl shows a power advantage over ttl. since the translators in table 1 have either ttl inputs or outputs, the power will increase slightly with frequency, but not as much as pure ttl devices. cr0 cr1 z0 z1 z2 z3 operation l l l h h h no errors h l h l h h type 1 error (t1) l h h h l h type 2 error (t2) h h h h h h type 3 error (t3)
3 www.fairchildsemi.com AN-784 power supply and noise considerations the primary consideration with mixed voltage, dual rail translators is to insure maximum noise protection between the ttl and ecl ground. the ecl bandgap circuit (shown in figure 2) is used to generate internal reference voltages. the internally generated reference voltage used to set the input and output threshold levels is called v bb . the poten- tial generated to control the level of the active current source is called v cs . these reference voltages (v bb and v cs ) set up by the bandgap circuitry are referenced to the ecl ground (v cc ). any noise on this ground will be injected into the reference voltages (v bb and v cs ) produc- ing reduced noise immunity. this implies that a stable, noise free ecl ground is needed. figure 2. ecl bandgap circuit figure 3. ecl error capture circuit ground bounce has been a concern of ttl designers for many years. figure 4 shows the ttl totem pole output structure. the intrinsic inductance in the ground lead (ttl gnd) and power lead (v ttl ) are labeled as l1 and l2, respectively. in order to switch from high to low, current (marked i1 in figure 4) must flow through q3 and l2 to dis- charge the load capacitance. as this current changes, a voltage is developed across the inductor l2 (recall: v2 = l2 (dl2/dt). since the inductor (l2) is between system ground and the device ground, there will be a voltage drop between them. this voltage difference between device and system ground will cause the device input and output levels to be offset because they are referenced to the internal device ground. the devices which are driving inputs or being driven by the outputs are referenced to the system ground (ttl gnd in figure 4). this effect is known as ground bounce.
www.fairchildsemi.com 4 AN-784 power supply and noise considerations (continued) figure 4. ttl totem pole output to insure maximum noise protection, it is recommended that the ecl and ttl ground planes on the printed circuit board (pcb) are run independently, and are only con- nected back at the low impedance source of the power supply. likewise separate power planes will be used for the ttl positive supply (v ttl ), ecl negative supply (v ee ), and ecl output load power supply (v t ). this leads to five layers of a multi-layer pcb being dedicated to power planes. additional layers, either internal or on the surface, can be used to run signal lines. figure shows a typical lay- out for a seven layer ttl/ecl pcb. signals are run on both sides of the board. figure 5. pc board power planes consideration should be made with regard to the power up sequencing of translators. table 3 describes the conditions observed for the various translators when ecl or ttl power is lost. control pins should be driven by power up referenced sig- nals, so that during power up sequencing, the output enable pins are driven to the disable state. design considerations translator pin connections dual rail translation implies that both positive (v ttl ) and negative (v ee ) voltage supplies must be used. these volt- ages are typically + 5v and ? 5v respectively. v cc and v cca pins are used for the ground connection to 0v. the f100k 300 series translators offer a 28-pin plastic leadless chip carrier (plcc) package for surface mount capability to reduce board space. this package includes three v ees pins which are used to dissipate heat from the package. these pins are connected internally through the substrate to v ee . it is recommended that these pins be connected to the v ee power plane and never to v cc , v cca , or v ttl . translator location when using ecl with ttl or cmos, it is important to group cmos and ttl devices away from the ecl devices. this will reduce the possibility of corruption of ecl signals caused by noisy ttl or cmos switching. translators with ttl outputs should be grouped with the ttl devices on the printed circuit board (pcb), and translators with ecl outputs should be grouped with the ecl devices. table 3. output state under power loss layer 1 signal layer 2 ttl ground layer 3 ttl + 5v (v ttl ) layer 4 vt layer 5 ecl ? 4.5v (v ee ) layer 6 ecl 0.0v (v cc ) layer 7 signal product loss of v ttl loss of v ee ecl output state ttl output state ecl output state ttl output state 100324 v oh n/a v oh n/a 100325 n/a hi-z n/a hi-z 100329 v oh hi-z v oh hi-z 100395 n/a hi-z n/a hi-z
5 www.fairchildsemi.com AN-784 applications some of the many uses for ecl/ttl translators are: high speed cache memory: figure 6 shows a two way set associative cache system. data is transferred from the ecl memory to cache with the use of a single 8-bit 100328 bidirectional translator. once the data reaches the cache, it can be moved to the microprocessor quickly for manipula- tion. since the data bus is a two way communication sys- tem, a bidirectional translator is needed. the address bus, on the other hand, requires only a one way communication. this implies a unidirectional translator could be used to interface the address to ecl memory. it would take three hex 100324 devices for the 16-bit line shown in figure 6, but to reduce package count two 8-bit 100329 devices are used. the ecl memory based system allows reading and writing access within one clock cycle. since the memory is accessed quickly, the wait states produced by memory read and write are virtually eliminated which results in a faster operating system. memory division 1 block = 16 bytes 1 set = 2 blocks 8 sets in cache figure 6. two way set associative cache system peripheral interface applications: the 100395 9-bit translator is ideal for translation applications where an 8-bit data bus with parity is used. an example of this situation is shown in figure 7. in this case, ecl data and parity is transferred through an ecl controller and sent to the ecl- to-ttl translator. data and parity is then converted to ttl levels and sent through a cable to the peripheral unit (such as a printer) for parity checking and data transfer. the 9-bit ecl-to-ttl translator (100395) allows for an 8-bit data transfer and 1 bit for parity. the 9-bit function of the 100395 also enables the translation to be performed with one chip which reduces chip count and board space. these transla- tors also have a 64 ma output drive which is needed to drive the long length of cable associated with the printer hook up.
www.fairchildsemi.com 6 AN-784 f100k ecl dual rail translators applications (continued) figure 7. peripheral interface application ttl/cmos dynamic random access memories (drams): in instances where high speed ecl cpus are used, low power/low cost drams can be addressed as bulk storage for non-speed critical operations by interfacing the ecl cpu with dram via the 100329. this enables you to perform all of your high speed data processing tasks in ecl and use more readily available ttl/cmos drams for data storage. high speed coprocessor: a high speed ecl coproces- sor can be added to a lower speed processor for enhance- ment of high density computations. this will increase the speed and improve the overall system performance. the 100324 and 100325 would allow differential communica- tion to the ecl coprocessor and the differential ecl sig- nals give noise immunity from the surrounding ttl system. ecl bussing: all the translators give ttl systems the ability to use high speed and low emi ecl backplanes. ecl backplane applications typically use mixed technolo- gies off the backplane which means that quick and reliable translation is needed. refer to the ? ecl backplane design ? , applications note for additional information. graphics: the 100324/100329 give ttl to ecl conver- sion for use in high speed ecl graphics applications. the graphics will be in parallel form in the ttl state, converted to ecl then turned into serial form by either the 100341/ 100336 shift registers, before being fed to a high speed graphics driver. references d. bush, ? ecl backplane design ? , april 1991 applications note an-768. j. davis, ? operating ecl from a single positive supply ? , june 1991 applications note an-780 w. blood, ? mecl ? system design handbook ? , fourth edi- tion, 1988. copyright motorola, inc. ? f100k ecl logic databook and design guide ? , 1990 edi- tion. fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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